1. Field of the Invention
The present invention generally relates to a dynamic type semiconductor memory device, and more particularly, to a configuration for carrying out a refresh operation thereof.
2. Description of the Background Art
A memory cell in a dynamic type semiconductor memory device includes a capacitor, in which information is stored in a form of electric charges. In the dynamic type semiconductor memory device, in order to prevent destruction of storage data through leakage of electric charges inevitably caused in the memory cell capacitor, a refresh operation periodically restoring the storage data is carried out.
In the refresh operation, memory cells of one row in a memory cell array are brought into a selected state according to a refresh address, and data of the selected memory cells are sensed, amplified and restored. One of such refresh operation modes is called CBR refresh.
FIG. 30 is a signal waveform diagram showing operations in the CBR refresh mode. In the CBR refresh mode, a refresh instruction is set according to a CBR condition under which a signal /CAS (column address strobe) falls to an "L" level prior to falling of a signal /RAS (row address strobe). In response to falling of the signal /RAS, an internal control signal .phi.RAS is generated. The internal control signal .phi.RAS is a signal controlling circuitry (row decoder, sense amplifier and the like) relating to a row selecting operation in the memory device. Based on the internal control signal .phi.RAS, memory cells of one row are selected and data are restored. A refresh operation which is first carried out under the CBR condition is usually called "CBR refresh".
Setting the signal /RAS to an "L" level for a predetermined period (for 100 .mu.s as an example in FIG. 30) allows the CBR self refresh mode to be entered. A refresh request is generated by an internal timer at a predetermined time interval (16 .mu.s as an example in FIG. 30). In response to the refresh request, the internal control signal .phi.RAS is generated. According to the refresh request, the refresh address is generated from an internal address counter. The selecting operation of a row and the restoring operation according to the refresh address are carried out. The refresh mode carried out after a lapse of a predetermined period (for example, 100 .mu.s) is usually called "CBR self-refresh".
The CBR refresh and the CBR self-refresh are usually called self-refresh mode.
In the self-refresh mode, refreshing is automatically carried out within the memory device if only external control signals /RAS and /CAS are placed under a predetermined condition. It is not necessary to apply an external control signal for each refresh cycle. Since the refresh address is also generated in the memory device, it is not necessary for a control device such as an external DRAM controller to operate. From the standpoint of power consumption as an entire system, the self-refresh mode is preferred.
Such a self-refresh mode is generally used in a battery backup operation or the like carrying out a data holding operation.
In an operating waveform diagram of the self-refresh mode shown in FIG. 30, the signal /CAS is set to an "L" level during the self-refresh mode period similar to the signal /RAS. After a self-refresh instruction, the signal /CAS may be maintained in an arbitrary state. This is because, in the self-refresh mode, the internal control signal .phi.CAS controlling operations of circuitry relating to a column selecting operation is forcibly set to an "L" level of an inactive state while the signal /RAS is at an "L" level.
FIG. 31 is a diagram showing a simplified configuration of a general data processing system. In FIG. 31, the data processing system includes a central processing unit (CPU) 502 carrying out an operational processing according to a loaded program, a dynamic random access memory (DRAM) 506 serving as a main memory device of the data processing system, and a memory managing unit (MMU) 504 for managing access from CPU 502 to DRAM 506. MMU 504 carries out multiplexing of a row address and a column address to DRAM 506, generation of signals /RAS and /CAS, and the like.
The data processing system further includes a main power source 508, an auxiliary power source 510, and a power source switching circuit 512 selecting auxiliary power source 510 in place of main power source 508 when main power source 508 is in a power-off state and supplying a power supply voltage to CPU 502, MMU 504 and DRAM 506 from auxiliary power source 510. Main power source 508 may be a commercially available power source or a battery.
When main power source 508 is in a power-off state by the blackout or the like, power source switching circuit 512 is responsive to the power-off state for selecting the power supply voltage from auxiliary power source 510 to apply the same to respective units 502, 504 and 506. In response to the power-off state of main power source 508, CPU 502 has a process under execution interrupted and carries out necessary processings. After auxiliary power source 510 is selected by power source switching circuit 512, DRAM 506 enters a so called "battery backup operation mode". In this operation mode, according to an instruction from CPU 502, MMU 504 provides to DRAM 506 an instruction of self-refresh mode according to, for example, the CBR condition. In the meantime, only the data holding operation is carried out in DRAM 506.
Power source switching circuit 512 monitors only power-on/power-off of main power source 508 and carries out switching of power sources according to the monitor result. In the case where main power source 508 is a commercially available power source, numerous devices/apparatuses using the commercially available power source simultaneously operate, sometimes causing a voltage level of main power source 508 to be decreased temporarily. In this case, since power source switching circuit 512 does not detect a power-off state, power source switching circuit 512 does not switch power sources, and selects main power source 508. Since processings are carried out in the data processing system using the decreased power supply voltage, the system malfunctions because of decrease of a signal timing margin or the like.
In this case, it is also necessary to reduce power consumption of the data processing system and to promote recovery of main power source 508 to the power supply voltage level. However, in the conventional data processing system, even if the voltage level of main power source 508 was temporarily decreased, the data processing according to the program was carried out with no special processing being carried out, which partly delayed recovery of the voltage level of main power source 508.
When the power supply voltage is lowered, a data holding characteristic of memory cells in DRAM 506 is deteriorated. More specifically, as compared to the case where the power supply voltage is normal, data held by a memory cell disappears in a shorter time. However, in the conventional semiconductor memory device, a configuration is not provided which refreshes the memory cell data positively when the level of the power supply voltage is lowered. Therefore, accurate holding of data is not ensured.
When the self-refresh operation is designated, it is necessary to meet the CBR condition or the like in the conventional configuration. In this case, it is necessary to drive a plurality of control signals. As a result, many circuits operate, which makes it impossible to reduce power consumption.
For the self-refreshing operation, it is also necessary to carry out a complicated timing setting of CBR condition for external control signals.